![]() The cookie is set by GDPR cookie consent to record the user consent for the cookies in the category "Functional". The cookie is used to store the user consent for the cookies in the category "Analytics". This cookie is set by GDPR Cookie Consent plugin. The cookie is set by GDPR cookie consent to record the user consent for the cookies in the category "Advertisement". These cookies ensure basic functionalities and security features of the website, anonymously. Necessary cookies are absolutely essential for the website to function properly. Though some roadblocks standing in the way of progress toward future generations look more like high walls than hurdles, Moore’s Law continues to hold for the total IC industry. The powerful drive of the IC industry to innovate its way over and around technology barriers can never be underestimated, but there are some very dramatic shifts underway regarding how ICs are designed and manufactured. Some of the latest GPUs from Nvidia are neural network processing units (NPUs) designed specifically for AI and machine learning. ![]() Unlike microprocessors, GPUs and their highly parallel structure do not contain a significant amount of cache memory. High-end GPUs from Nvidia have incredibly high transistor counts. In the first half of 2020, Apple is expected to unveil an iPad Pro based on a new A13X processor. ![]() That rate includes as the most recent endpoint the A13 processor, with its 8.5 billion transistors. Transistor counts for Apple’s A series application processors used in its iPhones and iPads have increased at the annual rate of 43% since 2013. Intel stopped revealing details of transistor counts in 2017. Transistor count increases for the company’s server MPUs paused in the mid- to late-2000s but then started growing again at the rate of about 25% per year. Transistor counts in Intel’s PC microprocessors grew approximately 40% per year through 2010, but the rate dropped to half that in the years following. QLC combined with new 96-layer technology should enable 3D NAND to reach 1.5Tb density in 2020 with 128-layer technology leading to 2Tb chips. The maximum density for a 3D NAND chip is currently 1.33Tb for a 96-layer quad-level-cell (QLC) device. For conventional 2D planar NAND flash, the highest density on a single die available in January 2020 was 128Gb. The DDR5 standard still being finalized by JEDEC includes monolithic 24Gb, 32Gb, and 64Gb devices.Īnnual growth in flash memory densities remained at 55-60% per year through about 2012 but has since been around 30-35% per year. One year earlier Samsung initiated volume production of 12Gb DRAM chips, and 8Gb devices one year before that. Samsung began volume production with single-chip 16Gb DRAM devices near the end of 2016. For example, DRAM transistor counts were increasing at the average rate of about 45% per year through the early 2000s but slowed to about 20% through the 16Gb generation that appeared in 2016. Figure 1įactors such as power consumption and challenges associated with scaling limitations have cut into the transistor growth rates of some IC products during the last 10-15 years. IC Insights’ 2020 edition of The McClean Report (released in January) shows how over the past five decades, DRAMs, flash memories, microprocessors, and graphics processors have tracked the curve Moore predicted (Figure 1). It pertains to the growth rate of components per chip, but it is sometimes generalized to describe the exponential growth in raw computational power achieved with each new generation of ICs. The primary yardstick by which the IC industry measures its technological performance and progress remains Moore’s Law that states there is a doubling of the number of transistors per chip every two years.
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